Added Capabilities to InTimeĪs FPGAs and design flows become more complex, the number and difficulty of critical timing and performance issues increase exponentially. Unlike linting tools, Kabuto recommends fixes for bad timing paths at the register transfer level. It reads critical-path information and pinpoints corresponding source code segments, analyzes them and then proposes RTL fixes.įor instance, Kabuto can identify the need to pipeline a design, suggest the exact lines of code to be modified and ensure that dependencies are checked properly.
Kabuto, the Japanese term for “helmet,” protects FPGA designs from performance errors by recommending register transfer level (RTL) code fixes based on timing path and RTL code analysis. Introducing Kabuto for fixing RTL Code Performance It will offer continuous demonstrations of its complete product portfolio. at the Austin Convention Center in Austin, Texas. Plunify will exhibit at the Design Automation Conference (DAC) in Booth #1631 June 19-21 from10 a.m. “Our machine learning features for timing closure and optimizing FPGA designs enables our users to outperform their competitors,” remarks Harnhua Ng, Plunify’s chief executive officer and co-founder.
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Kabuto joins Plunify’s InTime™ for time closure and performance optimization to solve critical design problems for a variety of markets, including data center, advanced driver assistance systems and high-frequency trading.
Plunify®, supplier of field programmable gate array (FPGA) timing and performance software based on machine learning techniques, today introduced Kabuto™ to minimize and eliminate performance errors.